Semiconductor integrated circuits (ICs) are typically formed on semiconductor substrates in a manufacturing or fabrication process. Silicon wafers are usually employed to provide a common substrate for the components of the ICs. Numerous ICs (also called dies or chips) are formed on and in each wafer. The ICs formed on semiconductor substrates, such as silicon wafers, typically include a variety of basic electrical components, such as transistors, amplifiers, resistors, and capacitors, for example. It is desirable to verify that such integrated basic components are fabricated according to a design specification and have certain electrical properties or values (e.g., a specified gain, resistance, etc). However, an individual component usually cannot be readily tested after being integrated into a circuit.
In lieu of testing the integrated components (i.e. the components that are part of the ICs on the wafer that will be sold), “stand-alone” copies of such basic components are often tested. The stand-alone copies are typically fabricated in some separate location of the surface of the wafer not occupied by the dies or ICs formed on the wafer. Such stand-alone copies or “target components” have electrical properties or values of gain, resistance, and the like that are representative of such properties for their IC counterparts because they are fabricated using the same process (and typically during the same process). As such, it may be assumed that the parameters measured for the target components are similar to those of the non-tested integrated components. Thus, the test results of the stand-alone copies provide an indication of the electrical properties for the integrated components that will be sold. This type of quality control methodology is often referred to as “in-process electrical testing.”
During in-process electrical testing, a signal source and a measurement device (usually external) are electrically connected to the stand-alone target component to be tested, or the “device under test” (DUT). Electrical connection is typically effected via microprobes, one of which is attached to an end of a coaxial cable carrying a signal from the signal source (providing a test input signal), and another of which is attached to an end of a coaxial cable leading to the measurement device (collecting the output response from the target component).
On the wafer, the target component or DUT is electrically connected to pads. The microprobes contact the pads, thereby electrically connecting the signal source and the measurement device to the DUT. The measurement device is typically used to measure various response or performance parameters of the DUT (i.e. parameters which characterize the response or performance of the DUT). The pads and the DUT, collectively, form a “process monitor” or “device monitor,” sometimes referred to as a “tester.” Some of the wafer surface is typically reserved for such testers. This reserved surface usually cannot be utilized for devices forming part of the ICs.
Sometimes the leads to the DUT themselves hinder the measurement of the DUT itself because the leads exhibit physical characteristics that mask or obscure the physical characteristics of the DUT. Thus, to accurately measure the physical characteristics of the DUT, the physical characteristics of the leads, which are known as “parasitics,” must be understood so that they can be factored out to reveal the true characteristics of the DUT. The process of factoring-out or extracting parasitics is referred to as “de-embedding.” One method for de-embedding parasitics involves, for example, analyzing four different DUTs that are fabricated with the same process and in accordance with the same design specifications as the IC devices of interest. These four DUTs are widely-known to those skilled in the art as “short,” “load,” “open,” and “thru” DUTs.
It is through the probe pads that the physical characteristics of the DUTs are measured using external measuring equipment. From these measurements, the parasitics of the leads can be determined and applied in well-known fashion to de-embed the parasitics and reveal the “true” parameters of the nominal DUT. Although this technique for de-embedding parasitics is well known and widely used, its use is problematic in some applications. In particular, integrated circuits with conductive substrates (e.g., silicon substrates, etc.) that operate at high frequencies generate particularly strong parasitics that hinder the de-embedding process. Current radio frequency (RF) ground-signal-ground (GSG) pad patterns have high parasitics; many times due to low CMOS substrate resistively, for example. Such parasitics also may cause coupling between the two ports of the DUT, which makes de-embedding more difficult or not possible. Therefore, a need exists for ways to de-embed parasitics associated with DUT leads and measurement probes for devices formed on conductive substrates and that operate at high frequencies (e.g., GHz ranges).